1. Field of the Invention
The present invention is related to a differential output circuit, in particular, to a differential output circuit responsive to a pair of complementary input signals to output a pair of complementary output signals.
2. Description of the Related Art
Semiconductor integrated circuits often include differential output circuits, which are responsive to a pair of complementary input signals to output a pair of complementary output signals. Differential output circuits are very noise resistive, and their characteristics are almost free from the effects of inevitable manufacturing variation. These advantages promote wide use of the differential output circuits, such as receiver/transmitters of cellular phones.
Impedance matching is of importance for the differential output circuits to avoid waveform distortion of output signals. Japanese Unexamined Patent Application No. Heisei 9-162653 discloses a differential output circuit having a pair of MOS transistors whose sources are connected to VSS through an inductive element. The inductive element effectively cancels the parasitic capacitance of the differential output circuit, and thereby achieves impedance matching.
Japanese Examined Patent Gazette No. Heisei 7-16158 discloses a conventional differential output circuit which adopts a pass transistor logic technology, which uses not only gates of MOS transistors but also sources and drains for inputs of logic gates, for increasing the operation speed. Other advantages of the pass transistor logic are the simple design and the reduced power consumption.
FIG. 1 is a circuit diagram of the conventional differential output circuit. The conventional differential output circuit 102 receives a pair of complementary signals P and /P from a logic circuit 101 including N-channel MOS transistors MN13 to MN20. The logic circuit 101 receives input signals IA, IB, /IA and /IB, the input signals /IA and /IB being complementary to the input signals IA, IB, respectively. The logic circuit 101 functions as an XOR gate and develops signals P and /P, the signal P being the XOR of the input signals IA and IB, and the signal /P is complementary to the signal P.
The conventional differential output circuit 102 includes a pair of N-channel transistors MN11 and MN12, and a pair of P-channel transistors MP11 and MP12. The N-channel transistor MN11 and P-channel transistor MP11 are connected in series between a power supply terminal and an inverting input receiving the signal /P, while N-channel transistor MN12 and P-channel transistor MP12 are connected in series between a power supply terminal and a non-inverting input receiving the signal P. The P-channel transistors MP11 and MP12 respectively receive the signals P and /P on the gates thereof. The gates of the N-channel transistors MN11 and MN12 are connected to a power supply terminal. The conventional differential output circuit 102 develops a pair of output signals O and /O on the drains of the N-channel transistor MN12 and MN11, respectively.
Although the differential output circuit 102 includes P-channel transistors MP11 and MP12, which are generally inferior to N-channel transistors in the operation speed, the differential output circuit 102 enjoys fast operation speed. This is because the pull-up of the output signals O and /O are achieved by not only the P-channel transistors MP11 and MP12 but also the pull-up transistor of the logic circuit 101 (that is, the N-channel transistor MN13).
The wide bandwidth is of importance for differential output circuits. Therefore, a need exists to provide a differential output circuit having a wide bandwidth.